The eco32 family of 32-bit microprocessors is targeted at embedded control & computing and DSP applications. The family defines two ISAs:

  • eco32b: (base ISA) for general purpose control and computing with light DSP enhancements

  • eco32d: (DSP extension ISA) for 32-bit DSP and audio applications





Base DSP


eco32bl eco32dl

ISAs (Instruction Set Architectures)

Base ISA

The eco32b is a 32-bit microprocessor architecture for embedded control & computing applications. Main focus of the ISA definition is on high code density enabled through 16/32-bit variable length instruction coding and low power consumption enabled through the moderate number of registers.

The eco32b is a load/store architecture. All operands of computation instructions are either constants or contained in registers. Load/store instructions are used to transfer operands between registers and memory.

The eco32b ISA defines a generic and complete instruction set for efficient high level language compiler implementations. In addition it defines a set of DSP enhancement features that use the available processor resources (registers, multiplier) and do not add significantly to the size and complexity of processor implementations. With these features the eco32b is a good candidate also for applications with moderate DSP performance requirements. For higher performance DSP applications the eco32d ISA is available.


  • Harvard architecture with separate instruction and data buses

  • 4 GBytes instruction address space

  • 4 GBytes data address space

  • Variable length instruction coding with 16-bit and 32-bit opcodes

  • 16 interrupts (4 non-maskable, 12 maskable) with programmable start addresses

  • 16 x 32-bit general purpose registers

  • Separate 32-bit Stack Pointer

  • Native support for 8-bit, 16-bit and 32-bit signed and unsigned integer data types

  • Higher precision integer and float data types supported by multi-instruction sequences

  • Rich set of load/store addressing modes, including indirect with scaled index and update addressing

  • Little endian byte ordering

  • Load/store multiple instructions for code efficient copying and function prologue/epilogue

  • Bit manipulation & test instructions: set, clear, toggle & test

  • Bit field instructions: make, insert, signed/unsigned extract, 1-32 bits width, 0-31 bits offset

  • 32*32 multiply with high or low word result

  • 32-bit iterative divide instruction

  • Flexible debug interface to connect application specific debug modules

DSP enhancements

  • MAC (Multiply & Accumulate) and MAS (Multiply & Subtract) instructions

  • MAC/MAS instructions with 1-bit or 2-bit left-shift before accumulation

  • Clip instruction with programmable low/high boundaries

  • Direct and indirect auto update addressing modes for load/store instructions

  • 2 x 16-bit loop counters

DSP extension ISA

The eco32d is an extension of the eco32b base ISA and is fully backward compatible with the eco32b. Main target are 32-bit DSP and specifically audio applications. The DSP extension adds only a few special registers but no general purpose registers to the programming model of the eco32b. Main additions are addressing modes with memory source operands and special add/subtract instructions that improve the performance of audio and general DSP algorithms. With the same pipeline architecture and computation resources implementations of eco32d processors are only slightly larger than base ISA implementations.

The eco32d deviates from the puristic load/store architecture of the eco32b. Some performance critical extension instructions have one source operand in memory.

The instructions with additional addressing modes and the additional, special add/subtract instructions can't be used easily from high level languages. The targeted use model suggests hand optimized assembler routines for performance critical DSP functions using the special addressing modes and instructions. The less performance critical higher layers and control code is written in C and compiled to the eco32b base ISA instruction set.

Extension Features

  • Special add/subtract instructions with 1-bit left-shift of one source operand before the add/subtract operation

  • Additional addressing modes with one memory source operand for MAC/MAS and special add/subtract instructions

  • Three additional memory addressing modes: indirect with offset or direct/indirect update

  • Dual entries accumulation extension cache (patented) for sum-of-products calculation with 64-bit precision



The eco32bl light implementation is focused on high performance and moderate resource consumption. A 3 read-ports register-file makes sure that almost all instructions potentially can be executed in one cycle effective. A decoupled unit for instruction fetch and flow-instruction execution together with separate execution units for computation and for load/store instructions enable high pipeline throughput.

With 16/32-bit variable length instruction coding and a 32-bit instruction bus the average instruction fetch rate per cycle is > 1 and fills the decoupling buffer between the instruction fetch unit and the computation and load/store execution units. A filled buffer enables zero cycle effective execution time for flow change instructions (branch, jump, return).

Branch speculation, pre-fetching and conditional instructions minimize performance penalties of program flow changes. Average IPCs strongly depend on instruction sequences e.g. branches and operand dependencies. Performance optimized sequences can get close to an IPC of 1, highly optimized sequences with effective zero cycle flow change instructions can achieve IPCs > 1.


  • Size: ~7500 LEs on FPGAs

  • 32-bit/32-bit instruction/data buses

  • Register-file with 3/2 read/write ports

  • Max clock ~100Mhz on low end FPGAs

  • Average IPC (Instr. per Cycle) ~0.8

  • Single cycle effective MAC instructions with two register source operands

  • Barrel-Shifter, single cycle effective shift execution

  • Non-blocking, iterative hardware divide


The eco32dl light implementation has the same basic pipeline architecture as the eco32bl. Only difference is an extra execution unit for multiply/MAC instructions. To support this unit the register-file is upgraded to 4/3 read/write ports.


  • Size: ~9000 LEs on FPGAs

  • 32-bit/32-bit instruction/data buses

  • Register-file with 4/3 read/write ports

  • Max clock ~100Mhz on low end FPGAs

  • Average IPC (Instr. per Cycle) ~0.9

  • Single cycle effective MAC instructions with one register and one memory source operand

  • Barrel-Shifter, single cycle effective shift execution

  • Non-blocking, iterative hardware divide