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sf20 family of 16-bit processors |
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IntroductionThe sf20 is a 16-bit microprocessor architecture for embedded control & computing applications with limited code size requirements. Main focus of the ISA definition is on high clock rates and small core implementations. The sf20 is specifically targeted at FPGAs. With 20-bit fixed length instruction coding it provides excellent code density for an architecture with 16 general purpose registers and it exploits the fact that efficient 20-bit wide block RAMs are available in most FPGA architectures. Two ISAs are available:
ResourcesEvaluation_Package (contains free sf20bu) DetailsISAs (Instruction Set Architectures)Base ISAThe sf20b is a load/store architecture. All operands of computation instructions are either constants or contained in registers. Load/store instructions are used to transfer operands between registers and memory. The sf20b base ISA defines a generic and complete instruction set for efficient high level language compiler implementations. Features
ResourcesDSP extension ISAThe sf20d deviates from the puristic load/store architecture of the sf20b. Some performance critical DSP instructions have addressing modes with one source operand in memory Extension Features
Implementationssf20buThe sf20bu ultra light implementation is focused on low resource comsumption. A dual-ported RAM implements the general-purpose and most special registers. Instructions with two register source operands have 2 cycles effective execution time. A combined ALU/load/store unit has shared resources for computation and load/store instructions. Load/store instructions have 2 cycles effective execution time. Shift instructions are executed iteratively with 1 bit per cycle. Together this leads to an average IPC of ~0.5 which is still good enough for many embedded control applications. Features
Resourcessf20blThe sf20bl light implementation is focused on high performance and moderate resource consumption. A 3 read-ports register-file makes sure that all instructions potentially can be executed in one cycle effective. A decoupled unit for instruction fetch and flow-instruction execution together with separate execution units for computation and for load/store instructions enable high pipeline throughput. Branch speculation, loop cache and conditional instructions minimize performance penalties of program flow changes. Average IPCs strongly depend on instruction sequences e.g. branches and operand dependencies. Performance optimized sequences can get close to an IPC of 1, with the loop cache loop execution with IPCs > 1 is possible. Features
Resourcessf20dlThe sf20dl light implementation has the same basic pipeline architecture as the sf20bl. Only difference is an extra execution unit for multiply/MAC instructions. To support this unit the register-file is upgraded to 4/3 read/write ports. Features
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